科学网—到底什么是冯·诺伊曼结构？ - 姜咏江的博文.pdf

   对外经贸大学信息学院从事计算机体系结构研究的副教授姜咏江先生的大作《到底什么是冯·诺伊曼结构？》（见我从科学网拷屏的博文，本评论以2015年1月16日19点16分从科学网拷屏的博文为依据评论）看似一篇精心创作的科普博文，实际上错误百出，比民科还民科，我真不敢相信中国还有这种误人子弟的教师。这是我见到的最令我汗颜的高校教师。

   错误一，“冯·诺伊曼”是谁？ 你把冯·诺依曼往哪里放？

   错误二，“哈弗结构”又是什么东东？ 哈佛结构是不是错了？

   错误三，“哈弗将程序存储器和数据存储器分开了” 哈佛结构就是哈佛发明的？这种想当然的胡言乱语出在搞计算机体系结构的副教授之嘴，真是一大奇观。事实上，是哈佛大学的职工发明了哈佛结构，这位职工的名字不叫哈佛，这是众所周知的事实。

   错误四，“最重要的是冯·诺伊曼提出了“程序、数据存储”的思想方法”“现代计算机的各种形式，包括网络结构突破了“程序、数据存储”的思想方法了吗？没有，一个都没有！” 这个等于没有说。因为任何一种计算机结构都包含了程序和数据存储的方法。 哈佛结构比冯·诺依曼结构出现得更早，这种结构难道就没有程序和数据存储的方法了？事实上，没有任何一本权威教科书有这样表述。

   错误五，“不要过多地赞扬将程序存储器和数据存储器分开的“哈弗结构”吧，那只是在冯·诺伊曼伟大思想之下的一个设计改动而已，不要将这种小打小闹的设计改动就叫做“颠覆了冯·诺伊曼结构””。真是令人笑掉大牙，哈佛结构比冯·诺依曼结构更早出现，谁改进谁啊？事实上没有任何证据表明哈佛结构是冯·诺依曼结构的改进，两者可以看着是独立的出现的，并且哈佛结构出现得更早。

   可以肯定地说，姜咏江先生的大作《到底什么是冯·诺伊曼结构？》从术语错误到观点错误，在博文中比比皆是。我只是指出最容易证伪的错误。一个从事计算机体系结构研究的副教授还处在这种水平，真令人担忧其误人子弟。连计算机体系结构的基本功都没有，这样的教师能教出什么样的学生？

科学网—到底什么是冯·诺伊曼结构？ - 姜咏江的博文.pdf

补充：

下面补充来自外文网站的英文资料，感兴趣的可以看看。

冯.诺依曼结构

哈佛结构

冯.诺依曼结构介绍

The Von Neumann architecture, also known as the Von Neumann model and Princeton architecture, is acomputer architecture based on that described in 1945 by the mathematician and physicist John von Neumann and others in the First Draft of a Report on the EDVAC.^[1] This describes a design architecture for an electronicdigital computer with parts consisting of a processing unit containing an arithmetic logic unit and processor registers, a control unit containing an instruction register and program counter, a memory to store both data and instructions, external mass storage, and input and output mechanisms.^[1][2] The meaning has evolved to be any stored-program computer in which an instruction fetch and a data operation cannot occur at the same time because they share a common bus. This is referred to as the Von Neumann bottleneck and often limits the performance of the system.^[3]

哈佛结构介绍

The Harvard architecture is a computer architecture with physically separate storage and signal pathways for instructions and data. The term originated from the Harvard Mark I relay-based computer, which stored instructions on punched tape (24 bits wide) and data in electro-mechanical counters. These early machines had data storage entirely contained within the central processing unit, and provided no access to the instruction storage as data. Programs needed to be loaded by an operator; the processor could not boot itself.

Today, most processors implement such separate signal pathways for performance reasons but actually implement amodified Harvard architecture, so they can support tasks such as loading a program from disk storage as data and then executing it.

The IBM Automatic Sequence Controlled Calculator (ASCC), called Mark I by Harvard University’s staff,^[1] was a general purpose electro-mechanical computer that was used in the war effort during the last part of World War II.

The original concept was presented to IBM by Howard Aiken in November 1937.^[2] After a feasibility study by IBM’s engineers, Thomas Watson Sr. personally approved the project and its funding in February 1939.

从里面的历史事实可以看出，哈佛结构更早被提出和实现。

The principal advantage of the pure Harvard architecture—simultaneous access to more than one memory system—has been reduced by modified Harvard processors using modern CPU cache systems. Relatively pure Harvard architecture machines are used mostly in applications where tradeoffs, like the cost and power savings from omitting caches, outweigh the programming penalties from featuring distinct code and data address spaces.

• Digital signal processors (DSPs) generally execute small, highly optimized audio or video processing algorithms. They avoid caches because their behavior must be extremely reproducible. The difficulties of coping with multiple address spaces are of secondary concern to speed of execution. Consequently, some DSPs feature multiple data memories in distinct address spaces to facilitate SIMD and VLIW processing. Texas Instruments TMS320 C55x processors, for one example, feature multiple parallel data buses (two write, three read) and one instruction bus.

• Microcontrollers are characterized by having small amounts of program (flash memory) and data (SRAM) memory, with no cache, and take advantage of the Harvard architecture to speed processing by concurrent instruction and data access. The separate storage means the program and data memories may feature different bit widths, for example using 16-bit wide instructions and 8-bit wide data. They also mean that instruction prefetch can be performed in parallel with other activities. Examples include, the AVR by Atmel Corp and the PIC by Microchip Technology, Inc..

可以看出，哈佛结构在现在的CPU、DSP和微控制器上获得了广泛应用，哈佛结构才是目前应用最广的。

The shared bus between the program memory and data memory leads to the Von Neumann bottleneck, the limited throughput (data transfer rate) between the CPU and memory compared to the amount of memory. Because program memory and data memory cannot be accessed at the same time, throughput is much smaller than the rate at which the CPU can work. This seriously limits the effective processing speed when the CPU is required to perform minimal processing on large amounts of data. The CPU is continually forced to wait for needed data to be transferred to or from memory. Since CPU speed and memory size have increased much faster than the throughput between them, the bottleneck has become more of a problem, a problem whose severity increases with every newer generation of CPU.

The von Neumann bottleneck was described by John Backus in his 1977 ACM Turing Award lecture. According to Backus:

Surely there must be a less primitive way of making big changes in the store than by pushing vast numbers of words back and forth through the von Neumann bottleneck. Not only is this tube a literal bottleneck for the data traffic of a problem, but, more importantly, it is an intellectual bottleneck that has kept us tied to word-at-a-time thinking instead of encouraging us to think in terms of the larger conceptual units of the task at hand. Thus programming is basically planning and detailing the enormous traffic of words through the von Neumann bottleneck, and much of that traffic concerns not significant data itself, but where to find it.^[22][23]

The performance problem can be alleviated (to some extent) by several mechanisms. Providing a cache between the CPU and the main memory, providing separate caches or separate access paths for data and instructions (the so-called Modified Harvard architecture), using branch predictor algorithms and logic, and providing a limited CPU stack or other on-chip scratchpad memory to reduce memory access are four of the ways performance is increased. The problem can also be sidestepped somewhat by using parallel computing, using for example the Non-Uniform Memory Access (NUMA) architecture—this approach is commonly employed by supercomputers. It is less clear whether the intellectual bottleneck that Backus criticized has changed much since 1977. Backus's proposed solution has not had a major influence.^{[citation needed]} Modern functional programming and object-oriented programming are much less geared towards "pushing vast numbers of words back and forth" than earlier languages like Fortran were, but internally, that is still what computers spend much of their time doing, even highly parallel supercomputers.

可以看出，冯.诺依曼结构的缺陷需要引入修改的哈佛结构才能缓解。