虚空境界分享 http://blog.sciencenet.cn/u/depengchen 摄心神,致虚极,守静笃

博文

寄生参数提取 Parasitic extraction

已有 19190 次阅读 2017-10-30 17:15 |系统分类:科研笔记

寄生参数提取 Parasitic extraction


In electronic design automation, parasiticextraction is calculation of the parasitic effects in both the designeddevices and the required wiring interconnectsof an electronic circuit: parasitic capacitances, parasitic resistances and parasitic inductances, commonly called parasiticdevices, parasitic components, or simply parasitics.

在EDA中,寄生参数提取(寄生析出)是在设计设备和电子电路要求的线路相互连接着两者之间的寄生效应的计算,诸如寄生电容、寄生电阻、寄生电感等寄生效应的计算,一般地称之为寄生设备,寄生元件或者简称为寄生参量(寄生效应)。

寄生参数提取的主要目的是创建电路的一个精确模拟模型,这样,详细的仿真能精确模拟数字和模拟电路的响应。数字电路响应常用于填充数据库,为了信号延迟和负载计算,例如:时序分析;功率分析;电路仿真以及信号完整性分析。模拟电路常在更详细的试验台上运行来指示额外提取的寄生参数对设计的电路对其功能是否可行

The major purpose of parasitic extraction is tocreate an accurate analog model of the circuit, so that detailed simulationscan emulate actual digital and analog circuit responses. Digital circuit responsesare often used to populate databases for signal delay and loading calculationsuch as: timing analysis; power analysis; circuit simulation; and signalintegrity analysis. Analog circuits are often run in detailed test benchesto indicate if the extra extracted parasitics will still allow the designedcircuit to function.

Contents

Background

In early integrated circuits the impact of the wiring wasnegligible, and wires were not considered as electrical elements of thecircuit. However below the 0.5-micrometretechnologynode resistance and capacitance of the interconnects started making asignificant impact on circuit performance.[1] With shrinking process technologies inductanceeffects of interconnects became important as well.

在早期IC中,线路的影响是忽略不计的,线路不被视之为电路的一个电子单元,然而,互连线路的低于0.5mm的技术节点电阻和电容开始对电路产生了显著影响。随着紧缩的工艺技术,互连的电感效应也变得重要。

Major effects of interconnect parasitics include: signal delay, signalnoise, IR drop (resistive component of voltage).

互连寄生参数的额主要影响包括信号延迟,信号噪声,电阻压降(IR drop)(电压的电阻分量)

Interconnect capacitance extraction

互连电容提取

Interconnect capacitance is calculated by giving theextraction tool the following information: the top view layout of the design inthe form of input polygons on a set of layers; a mapping to a set of devicesand pins (from a Layout Versus Schematic run), and a crosssectional understanding of these layers. This information is used to create aset of layout wires that have added capacitors where the input polygons andcross sectional structure indicate. The output netlist contains the same set ofinput nets as the input design netlist and adds parasitic capacitor devices betweenthese nets.

Interconnect resistance extraction

互连电阻提取

Interconnect resistance is calculated by giving theextraction tool the following information: the top view layout of the design inthe form of input polygons on a set of layers; a mapping to a set of devicesand pins (from a Layout Versus Schematic run), and a crosssectional understanding of these layers including the resistivity of thelayers. This information is used to create a set of layout sub.wires that haveadded resistance between various sub-parts of the wires. The above InterconnectCapacitance is divided and shared amongst the sub-nodes in a proportional way.Note that unlike Interconnect Capacitance, Interconnect Resistance needs to addsub-nodes between the circuit elements to place these parasitic resistors. Thiscan greatly increase the size of the extracted output netlist and can causeadditional simulation problems.

Interconnect inductance extraction

互连电感提取


This section is empty.You can help by adding  to it.(July 2010)




Tools and vendors

工具和供应商

The tools fall into the following broad categories.

工具分为下面的广泛类别

  • Field     solvers provide physically accurate solutions. They calculate     electromagnetic parameters by directly solving Maxwell's equations. Due to high     calculation burden they are applicable only very small designs or to parts     of the designs.

场求解器提供了精确的物理解。它们通过直接求解Maxwell方程来计算电磁参数。由于高负荷的计算,它们仅应用于小规模的设计或者设计的一部分。

  • Approximate     solutions with pattern matching techniques are the only feasible approach     to extract parasitics for complete modern integrated circuit designs.

对完整的现代IC设计提取寄生参数,用模式匹配技术近似求解释是唯一可行的方法。

ANSYS Q3D Extractor (我正在用,希望同行多多指点哦。)

ANSYS Q3D Extractor uses method of moments (integral equations)and FEMs to compute capacitive, conductance, inductance and resistancematrices. It uses the fast multipole method (FMM) to accelerate thesolution of the integral equations. Outputs from the solver include current andvoltage distributions, CG and RL matrices.[2][3]

ANSYS Q3D Extractor使用了矩量法(积分方程)和有限单元法来计算电容、电导、电感和电阻矩阵。它使用了快速多极法(FMM)来加速积分方程的求解。求解器的输出包括电流和电压分布,电容电导CG和电阻电感矩阵。

FastCap, FastHenry(我正在用,希望同行多多指点哦。)

FastCap and FastHenry, from MIT (MassachusettsInstitute of Technology) are two free parasitics extractor tools forcapacitance, and inductance and resistance. Quoted in many scientific articles,they are considered golden references in their field. Source code, as well asWindows binary versions with viewer and editor are freely available from FastFieldSolvers.[4][5]

来自MIT的FastCap和FastHenry是两款用于电容、电感和电阻提取的自由寄生参数提出器。在许多科学论文中被应用。在这些领域中被当成黄金参考文献,源代码和带查看器与编辑器的视窗二进制版本也可以从FastFieldSolvers免费获得。

FasterCap (我正在用,希望同行多多指点哦。)

FasterCap, from FastFieldSolvers, is a free, opensource capacitance field solver, available for Windows and Linux OS, able tosimulate conductive structures embedded in piece-wise-constant, complexpermittivity dielectric media, automatic mesh refinement capability andin-core/out-of-core solver engine.

作为一款可用于视窗和Linux操作系统平台的,来自FastFieldSolvers的自由、开源的电容场求解器,FasterCap能够仿真计算内嵌于分段定常、复杂介电常数电解质的导体结构,具有自动化网格加密能力以及核内核外求解引擎。

StarRC

StarRC from Synopsys(previously from Avanti) is a universal parasitics extractor toolapplicable for a full range of electronic designs.[6]

来自Synopsys的StarRC是一款通用的寄生参数提取工具,可用于各种电子设计。

Quantus

Quantus from Cadence is a parasitic extractor tool forboth digital and analog designs and parasitics extraction check have to becarried out to prepare the design for postlayout verification.[7]

来自Cadence的Quantus是一款用于数字和模拟设计的寄生参数提取工具,,为布板后期校验设计而准备的寄生参数提取检查必须执行。

QuickCap NX

QuickCap NX from Synopsys is aparasitic extractor tool for both digital and analog designs.[8] It was based on QuickCap developedby Ralph Iverson of Random Logic Corporation, which was acquired by Magma andSynopsys.

来自Synopsys的QuickCap NX是一款用于数字和模拟设计额寄生参数提取工具。它基于Random Logic Corporation的Ralph Iverson开发的QuickCap,它可通过Magma和Synopsys来获得。

Calibre xACT3D

Calibre xACT3D from MentorGraphics is a parasitic extractor tool for both digital and analog designs.[9] It was based on PexRC developed byWangqi Qiu and Weiping Shi of Pextra Corporation, which was acquired by Mentor.

CapExt

CapExt from CapExt AS is a parasitic extractor toolfor extracting capacitance from PCBs based on Gerber files.[10]

See also

References

1.  "Automatic LayoutModification", by Michael Reinhardt, p.120

2.  MITComputational Prototyping Group

3.  ANSYSQ3D Extractor

4.  MITComputational Prototyping Group

5.  FastFieldSolvers

6.  StarRC

7.  QuantusQRC Extraction Solution

8.  QuickCap

9.  CalibrexACT3D

10.CapExt

https://en.wikipedia.org/wiki/Parasitic_extraction




https://blog.sciencenet.cn/blog-338872-1083052.html

上一篇:深度学习与地球物理反演之关系 E4D
下一篇:centos7中yum安装ntfs-3g
收藏 IP: 113.247.167.*| 热度|

0

该博文允许注册用户评论 请点击登录 评论 (0 个评论)

数据加载中...

Archiver|手机版|科学网 ( 京ICP备07017567号-12 )

GMT+8, 2024-7-17 00:41

Powered by ScienceNet.cn

Copyright © 2007- 中国科学报社

返回顶部