[笔记，趣闻，科普] 三维（3D）电子技术，晶体管

三维（3D）电子技术： three-dimensional electronics

玻尔兹曼暴政： Boltzmann tyranny

垂直纳米线： vertical-nanowire

异质结： heterojunction

隧道晶体管： tunnelling transistors

   2023-08-16，Nature 提倡像“盖大楼”一样去研发新的晶体管。

   果然，2024 年 Nature Electronics 就推出来几种“大楼”式样的新型晶体管。

   其中， MIT 的博士后邵彦杰（Yanjie Shao）盖的纳米楼最漂亮！他们使用锑化镓和砷化铟，设计了隧穿场效应晶体管。

   “邵彦杰制造了直径仅为6纳米的纳米线异质结构，采用只有几纳米宽的垂直纳米线（堪比DNA链的宽度），可以提供与最先进的硅晶体管相当的性能，同时在比传统硅器件低得多的电压下高效运行。极小的尺寸将使更多此类晶体管能够封装到芯片上，从而满足电子设备快速、强大且更节能的需求。”

https://www.kepuchina.cn/article/articleinfo?business_type=100&classify=0&ar_id=552720

   外行，看不懂。不知道下面的【机器翻译】是否正确？

https://www.nature.com/articles/s41928-024-01310-0

   Numerous developments in three-dimensional electronics have emerged in 2024, creating new opportunities for conventional and emerging electronic systems.

   Back in June, we selected three-dimensional (3D) electronics as our technology of the year for 2024. Building vertically — be it by stacking silicon chips with advanced packaging technologies or using two-dimensional (2D) semiconductors to achieve monolithic 3D integration — is a technique that can increase device density and create novel computational systems. And it is a key approach for both the immediate development of computer chips and the longer-term development of emerging electronic devices.

   【机器翻译】2024年，三维电子技术出现了许多发展，为传统和新兴电子系统创造了新的机遇。

   早在6月，我们就选择了三维（3D）电子技术作为2024年的年度技术。垂直构建——无论是通过堆叠具有先进封装技术的硅芯片，还是使用二维（2D）半导体来实现单片3D集成——都是一种可以提高器件密度并创建新型计算系统的技术。这是计算机芯片近期发展和新兴电子设备长期发展的关键途径。

https://www.nature.com/articles/s41928-024-01310-0

   以下是三种新型的晶体管。

一、三维集成金属氧化物晶体管

图1  原文 Fig. 1: 3D monolithic integration of In2O3 TFTs.

https://www.nature.com/articles/s41928-024-01205-0/figures/1

https://www.nature.com/articles/s41928-024-01205-0

   a–c, Two-dimensional and 3D schematic representations of BG (a), TG (b) and DG (c) transistors. d, 3D schematic representation of 10-S DG transistors on an Si/SiO2 substrate.

   【机器翻译】a–c，BG（a）、TG（b）和DG（c）晶体管的二维和三维示意图。d、 Si/SiO2 基板上10-S DG晶体管的3D示意图。

   thin-film transistor (TFT) ： 薄膜晶体管

   bottom-gate (BG) and top-gate (TG) ： 底栅（BG）和顶栅（TG）

   dual-gate (DG) transistors (Fig. 1c) ： 双栅极（DG）晶体管（图1c）

二、垂直生长的金属纳米片与原子层沉积电介质集成，用于具有亚纳米电容等效厚度的晶体管

图2  原文 Fig. 4: MoS2 transistors with 2 nm HfO2/Pd based as top-gate dielectric and electrode.

https://www.nature.com/articles/s41928-024-01202-3/figures/4

https://www.nature.com/articles/s41928-024-01202-3

   a, Schematic diagram of top-gate MoS2 transistors using 2 nm HfO2 (sub-1 nm CET) and 2D Pd as top-gate dielectric and electrode. b, The dual-sweep transfer curves measured under different Vds from 0.1 to 1.0 V. c, Corresponding output curves under different gate bias (Vgs = 1 to −1 V). d,e, The benchmark of the normalized gate hysteresis13,15,18,26,27,49,50,51,52 (d, Norm. ΔVH) and leakage current13,15,18,19,21,26,29,49,50,51 (e) as a function of CET value for the ALD-Pd gated MoS2 FETs compared to state-of-the-art representative 2D FETs.

   【机器翻译】a、 使用2nm HfO2（亚1nm CET）和2D Pd作为顶栅电介质和电极的顶栅MoS2晶体管的示意图。b、 在0.1至1.0 V的不同Vds下测量的双扫描传输曲线，c、 以及在不同栅极偏压（Vgs =1至-1 V）下的相应输出曲线。d、 e，与最先进的代表性2D FET相比，ALD-Pd 门控 MoS2 FET的归一化栅极滞后电阻13,15,18,26,27,49,50,51,52（d，范数ΔVH）和漏电流13,15,18,19,21,26,29,49,50,51 （e）的基准是CET值的函数。

   capacitance-equivalent thickness (CET) ： 电容等效厚度

   atomic-layer deposition (ALD) ： 原子层沉积

   Pd, Palladium ： 钯

三、博士后邵彦杰：具有极端量子限制的缩放垂直纳米线异质结隧穿晶体管

图4  原文 Fig. 1: Ultra-scaled vertical-nanowire device design.

https://www.nature.com/articles/s41928-024-01279-w/figures/1

https://www.nature.com/articles/s41928-024-01279-w

   a,b, Heterostructures in the fabrication of a heterojunction Esaki diode (a) and a tunnelling transistor (b). c,d, False-coloured 30°-tilted SEM images of vertical nanowires in the Esaki diode (c) and the tunnelling transistor (d), which were fabricated by dry-etching and citric acid:H2O2 wet-etching with DInAs of around 6 and 8 nm at the tunnelling junction, respectively. e,f, Schematics of the finished device structures for the vertical-nanowire Esaki diode (e) and vertical-nanowire tunnelling transistor (f). Lg denotes the gate length, which is around 50 nm. W denotes tungsten, the gate metal. g,h, Schematic energy band diagrams for a vertical-nanowire diode and a vertical-nanowire transistor along the cut lines A–A' (e) and B–B' (f). Ec, Ev, Ef,S and Ef,D denote the lowest conduction sub-band, the highest valence sub-band, the source Fermi level and the drain Fermi level, respectively. Inset of h, Fermi–Dirac distribution for a finite temperature in the source. E and P denote the energy and occupation probability, respectively. Scale bars, 20 nm (c,d).

   【机器翻译】a、 b、异质结Esaki二极管（a）和隧道晶体管（b）制造中的异质结构。c、 d，Esaki二极管（c）和隧道晶体管（d）中垂直纳米线的假色30°倾斜SEM图像，分别通过干法蚀刻和柠檬酸：H2O2 湿法蚀刻在隧道结处制备，DInAs约为6和8 nm。e、 f，垂直纳米线Esaki二极管（e）和垂直纳米线隧穿晶体管（f）的成品器件结构示意图。Lg表示栅极长度，约为50nm。W表示栅极金属钨。g、 h，沿切割线a-a’（e）和B-B’（f）的垂直纳米线二极管和垂直纳米线晶体管的能带示意图。Ec、Ev、Ef,S 和 Ef,D 分别表示最低导带、最高价带、源极费米能级和漏极费米能级。h插图，源中有限温度的费米-狄拉克分布。E和P分别表示能量和占用概率。比例尺，20 nm（c，d）。

参考资料：

[1] Wei Cao, Huiming Bu, Maud Vinet, Min Cao, Shinichi Takagi, Sungwoo Hwang, Tahir Ghani, Kaustav Banerjee. The future transistors [J]. Nature, 2023, 620(7974): 501–515.   16 August 2023

doi:  10.1038/s41586-023-06145-x

https://www.nature.com/articles/s41586-023-06145-x

[2] Editorial, Build it up again [J]. Nature Electronics, 2024, 7(11): 935.

https://www.nature.com/articles/s41928-024-01310-0

[3] Saravanan Yuvaraja, Hendrik Faber, Mritunjay Kumar, Na Xiao, Glen Isaac Maciel García, Xiao Tang, Thomas D. Anthopoulos, Xiaohang Li. Three-dimensional integrated metal-oxide transistors [J]. Nature Electronics, 2024, 7(9): 768-776

doi:  10.1038/s41928-024-01205-0

https://www.nature.com/articles/s41928-024-01205-0

[4] Lei Zhang, Zhaochao Liu, Wei Ai, Jiabiao Chen, Zunxian Lv, Bing Wang, Mingjian Yang, Feng Luo,  Jinxiong Wu. Vertically grown metal nanosheets integrated with atomic-layer-deposited dielectrics for transistors with subnanometre capacitance-equivalent thicknesses [J]. Nature Electronics, 2024, 7(8): 662-670

doi:  10.1038/s41928-024-01202-3

https://www.nature.com/articles/s41928-024-01202-3

[5] 科普中国，2024-12-03，实现重要概念突破！MIT中国博后研制超高效3D晶体管

https://www.kepuchina.cn/article/articleinfo?business_type=100&classify=0&ar_id=552720

[6] Yanjie Shao, Marco Pala, Hao Tang, Baoming Wang, Ju Li, David Esseni, Jesús A. del Alamo. Scaled vertical-nanowire heterojunction tunnelling transistors with extreme quantum confinement [J]. Nature Electronics, 2024,

doi:  10.1038/s41928-024-01279-w

https://www.nature.com/articles/s41928-024-01279-w

相关链接：

[1] 2023-09-09 17:05，[小资料] FinFET（鳍式场效应晶体管 fin field effect transistor）

https://blog.sciencenet.cn/blog-107667-1402038.html

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