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本文为印度Rourkela国立研究院(作者:Arifa Parveen)的学士论文,共48页。
本课题旨在设计一种采用Verilog HDL的32位ISA(指令集结构)数字信号处理器及其在FPGA(现场可编程门阵列)中的实现。处理器使用统一的32位长度指令集演示,其中包含的指令分为三种格式,即寄存器、立即数和跳转型指令。该项目详细描述了MAC、控制模块、算术和逻辑单元、内存单元、寄存器文件、程序计数器、数据寄存器、多路复用器、ALU控制、符号扩展器等各个模块的设计和仿真,以及实例化所有上述模块的主模块。为了演示的目的,处理器被用于计算两个输入序列的卷积,从而利用所有三种指令格式。通过仿真,在Xilinx-ISE模拟器上进行了原理图生成和时序分析。各个模块在Spartan 3E系列XC3S500E FPGA板上实现和测试。
The project aims at designing a Digital Signal Processor with 32-bit ISA (Instruction SetArchitecture) using Verilog HDL and the implementation of its components in FPGA (Field Programmable Gate Array). The processor is demonstrated using uniform 32-bit length instruction set containing instructions that are categorized into three formats, referred to as Register, Immediate and Jump typeinstructions. The project gives detailed description of design and simulation of the individual modules like the MAC, control module, arithmetic and logic unit, memory units, register file, program counter, data registers, muxes, ALU control, sign extender and the main module instantiating all formerly mentionedmodules. For demonstration purposes, the processor is instructed to find theconvolution of two input sequences, thus making use of all three instructionformats. After simulation, schematics generation and timing analysis is carried out in Xilinx ISE simulator. The individual modules are implemented and tested in Spartan 3E family XC3S500E FPGA board.
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