Naveen Kumar Macha 研究小组：未来计算机的引领者！

以 Naveen Kumar Macha 为主要研究人员的 UMKC Nano-Computing Group

https://computing-lab.com/our-team/

一群朝气蓬勃的年轻人，学术领头人（PI，principal investigator）是 Dr. Mostafizur Rahman

https://computing-lab.com/group/dr-mostafizur-rahman/

   看过他们的网页介绍之后，不禁想起来当年的巴丁（John Bardeen）和布莱顿（Walter Houser Brattain），当年的基尔比（Jack St. Clair Kilby）。

   有理由猜想：他们就是未来计算机新技术的开拓者！

   了不起的一群年轻人！

   主要研究人员 Naveen Kumar Macha 的“Computing With Wires用导线做计算”为名被列为未来计算机技术的4个奇妙/奇怪途径之一。请看2018年1月IEEE Spectrum刊出的《4 strange new ways to compute》。

转载他们的三个研究方向的网页如下：

（1） Crosstalk Computing

https://computing-lab.com/crosstalk/

Logic with Wires: New Computing Direction Leveraging Interconnect Crosstalks

   Device, interconnect scaling and interconnection bottleneck are among the major challenges for CMOS scaling. Furhtermore, signal integrity issues like crosstalk- leakage of charge between capacitively coupled nets among neighboring signal lines, is becoming inexorable. We propose to astutely turn this detrimental effect into an advantage by engineering the interference among signal lines. Our proposal can potentially solve scaling challenges by reducing device and interconnect scaling requirements while complying with existing manufacturing paradigm. Central to our approach is the deterministic emulation of aggressor-victim scenarios in metal lines to achieve logic computation. As a result of input transitions on the aggressor nets, summation of aggressor nets charges is introduced on the victim net. The summation signal on victim net serve as outputs for logic gate, or used to control a pass transistor to get desired logic output. Depending on the boolean logic being computed, this sum of charges seen by victim net is controlled primarily by engineering the capacitance between aggressors and victims and by synchronous clocking. We have implemented all basic gates including NAND, NOR, AND, OR and XOR, and arithmetic circuits following this principle. Our results indicate huge potentials for compact and low-power computing using the proposed approach. 

（2） 3-D Integration

https://computing-lab.com/3-d/

Fine Grained Transistor-Level 3-D Integration

   Migration of traditional 2-D CMOS to 3-D has been elusive, since inherent customization requirements of CMOS circuits are not compatible for fine-grained 3-D. Partial attempts for 3-D CMOS with die-die and layer-layer stacking show incremental density benefits, but retain same CMOS scaling challenges, and add new constraints. In contrast to CMOS that evolved focusing on device centric mindset, where devices are scaled first, and circuit and layouts are optimized as afterthoughts, our research focus is on a nanoscale fine-grained 3-D integrated circuit fabrics that can provide  integrated solutions for all nanoscale technology aspects. Key to our 3-D  integration is the design of core fabric components that synergistically help to address device, circuit, connectivity, thermal and manufacturing issues in an integrated 3-D compatible manner.

   We are working on two different transistor level 3-D integration approaches using vertical (Skybridge) and horizontal nanowires (SN3D). Skybridge focuses on new device, circuit and integration concepts, whereas SN3D uses 3-D specific CMOS circuit style and integration schemes. Key to both approaches are unique architected fabric components that enable circuit implementation, routing and heat management in 3-D.

   Both designs achieve tremendous benefits compared to state-of-the-art CMOS technologies. Our bottom up evaluation method using TCAD Process, Device and HSPICE circuit simulations accounting for process parameters, material properties, nanoscale transport, 3-D circuit style, layout and parasitics reveals 24.6x density and 13.25x performance/watt benefits compared to CMOS for a 4-bit CLA, and 4.6x density, 4.2x active power and 51.2x leakage power benefits with comparable performance for Skybridge RAM in comparison to CMOS SRAM at 16nm.

   Our thermal evaluation include Finite Element Model based modeling and analysis, analytical modeling of fabric components and HSPICE simulations of 3-D circuits. Our simulation results show effectiveness of architected 3-D heat extraction features in reducing heat to reference temperature.

（3） In-Memory Computing

https://computing-lab.com/mvl/

In-Memory Multi-Valued Computing using Magneto-Electric Devices

   Multi-valued computing can yield significant benefits compared to binary computing due to greater capacity and compressed encoding of information. Emergence of nanoscale devices that allow information encoding, computation and communication in multi-valued domain, provide an unexplored arena for efficient multi-valued logic (MVL) implementation. Moreover, it can provide unique opportunities for Non-Von Neumann computing and eliminating Von-Neumann memory bottleneck.

   A key problem in moving towards MVL computing so far has been the complexity of MVL logic decomposition. Traditional approaches result in expressions that are very difficult to implement in hardware and ultimately yield little or no benefit when compared with Boolean. We are researching  a new approach for MVL decomposition combining linear regression and pattern matching algorithms to obtain simplified linear expressions for any arbitrary MVL function. The linearization process can scale with circuit size and can be mapped to any technology. 

   For hardware implementation, native properties of emerging devices such can be used to map the linear equations and selecting conditions in hardware. Our technology independent hardware implementation of a quaternary adder revealed huge potentials for area, power and performance savings; for a quaternary adder, our results show at-least 62.5% saving in switching components vs. binary CMOS.

   The new MVL decomposition and circuit implementation scheme combined with novel magneto-electric non-volatile devices can lead to Non-Von Neumann computing paradigm where computing elements can learn and can be reused for later usage without requiring memory access. The in-memory computing approach can reduce memory bottleneck and ultimately lead way for data mining, intelligent processing and neuromorphic processing. 

建议我国也成立这样研究小组，为未来的集成电路和计算机的发展做出新的贡献！

凯利（Mervin Joe Kelly），肖克利（William Bradford Shockley），达默（Geoffrey W. A. Dummer），或许就在我国。

相关资料：

[1] The Nobel Foundation, The Nobel Prize in Physics 1956

https://www.nobelprize.org/prizes/physics/1956/summary/

   The Nobel Prize in Physics 1956 was awarded jointly to William Bradford Shockley, John Bardeen and Walter Houser Brattain "for their researches on semiconductors and their discovery of the transistor effect."

[2] The Nobel Foundation, The Nobel Prize in Physics 2000

https://www.nobelprize.org/prizes/physics/2000/summary/

   the other half to Jack S. Kilby "for his part in the invention of the integrated circuit."

[3] The Silicon Engine, A Timeline of Semiconductors in Computers, Timeline

https://www.computerhistory.org/siliconengine/timeline/

[4] William Bradford Shockley -  National Academy of Sciences

http://www.nasonline.org/member-directory/deceased-members/50509.html

http://www.nasonline.org/publications/biographical-memoirs/memoir-pdfs/shockley-w.pdf

[5] Dr. John Bardeen Member -  National Academy of Sciences

https://www.nae.edu/29733/Dr-John-Bardeen

https://www.nae.edu/188639/JOHN-BARDEEN-19081991

相关链接：

[1] 2019-07-13，有关 Mervin Joe Kelly 先生的网页

http://blog.sciencenet.cn/blog-107667-1189385.html

[2] 2019-07-07，有关 Geoffrey W. A. Dummer 先生的网页

http://blog.sciencenet.cn/blog-107667-1188470.html

[3] 2019-07-24，Naveen Kumar Macha 资料与网页

http://blog.sciencenet.cn/blog-107667-1190979.html

[4] 4 STRANGE NEW WAYS TO COMPUTE,作者: Moore, Samuel K.,IEEE SPECTRUM,卷: 55,期: 1,页: 10-11, 出版年: JAN 2018 

https://ieeexplore.ieee.org/document/8241695

https://spectrum.ieee.org/nanoclast/computing/hardware/4-strange-new-ways-to-make-a-computer

[5] 闵应骅，2018-01-12，放开思路，重振计算科学技术 (180112) 精选

http://blog.sciencenet.cn/blog-290937-1094444.html

   密苏里大学堪萨斯城分校的Naveen Kumar Macha和他的团队

   Macha他们发现，适当安排连线可以出现类似的逻辑行为。譬如三根平行线，给旁边的一根或两根线一个电压，就会在中间那一根上引起一个串扰，这不就是一个或门吗？明智地增加一个晶体管，他们构建了与门、或门、异或门，以及一个有进位功能的电路。这四种电路都比相应的CMOS电路更少的晶体管和少得多的芯片面积。

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